This application claims priority from Indian Application for Patent No. 1041/Del/2001, filed Oct. 10, 2001, and entitled AN IMPROVED FRACTIONAL DIVIDER.
This invention relates to an improved fractional divider that is completely programmable, enables high resolution, and does not utilize any analog components.
A fractional divider provides a precise division of an input clock signal by a real number value K that typically includes an integer value and a fractional value. Fractional dividers are widely used in frequency synthesizers and clock recovery circuits.
In these applications the fractional divider is designed to be programmable over a range of values. Often, it is also important to ensure that the output signal is stablexe2x80x94owing to which a purely digital solution is preferred over one that uses analog techniques.
U.S. Pat. No. 6,157,694 describes a fractional frequency divider that implements a fixed frequency division. The fractional division is obtained by changing the phase of the frequency to the divider. Multiple clock signals having the same frequency but differing in phase are generated from the input signal. A delay line can be used to produce the different clock phases. The multiple clock signals are applied to the inputs of a multiplexer. The output of the multiplexer is fed to a constant integer value divider. A Finite State Machine (FSM) controls the selection inputs of the multiplexer to selectively apply different clock signals at appropriate times to the input of the divider to obtain the fractional division. The FSM can be preprogrammed or programmable. This invention utilizes an analog approach, which may be prone to noise. Further, the resolution possible for using this approach is limited, as the number of phase-shifted clocks that can be generated in practical terms is limited.
U.S. Pat. No. 3,959,737 is related to field of frequency synthesis. It employs the method of clock inhibition to achieve fractional frequency division. The basic philosophy in working of the fractional division is inhibition of the clock pulse to a divider that stretches the output clock period. In this invention this is achieved by configuring the controllable pre-scaler to K or K+1. The pre-scaler control circuit ensures that the control pulse is generated so that there are no timing related issues in high-speed division. The programmable counter controls one of the inputs to the OR gate and periodically configures the pre-scaler in divide by K or K+1. The scheme is limited where a very-fine fractional division is required. To get a particular value of fractional division, programming of at least three registers is required. For some pre-defined fractional divisions a look up table is provided. But it becomes complex to manage the fractional divisions using software. All the counters are re-initialized after the count is complete. This does not allow a fractional factor to be carried out for subsequent divisions. This creates problems in applications where an accurate fractional division is required.
U.S. Pat. No. 4,573,176 employs a fractional divider that achieves a division factor of either 2 or 2+1/N. The division factor of 2+1/N is achieved by dropping a clock pulse every N clock cycles. The fractional divider consists of D-type flip-flops and OR gates. The D-flip-flop is configured as a divide by 2. The output of this flip-flop is the output of a fractional divider and is fed to a programmable divider. The programmable divider is configured for any division by the configuration bus. The flip-flop gives a divide by 2 clock to the programmable divider. The fractional divider is configured in 2+1/N mode when the mode control is at logic xe2x80x980xe2x80x99. The clock input to the divide by 2 flip-flop is inhibited for one clock cycle in one division cycle. This effectively makes the programmable divider a 2N+1 divider, where N is the current programmed value in the programmable divider.
The disadvantage of this approach is that fractional division, as discussed in the ""176 patent can be configured only as 2+1/N. This scheme cannot be used where the fractional division is to be dynamically configured.
U.S. Pat. No. 6,127,863 discusses an efficient fraction division algorithm. The patent deals with modifications in the conventional fractional division to get an efficient fractional division (EFD) of M/(2N+K). The EFD employs N full adders, where the output Y of the full adder is coupled to an associated one of N registers or accumulators. The output of each accumulator is fed back to input of the corresponding full adder. The full adder also includes another set of accumulators, which couple the carryout or the complimented carry out signals of the full adder back to the frequency control inputs of the full adders. The multiplexers are used to select whether carry signals or complimentary carry out signals or the external signals are to be fed back to the frequency control inputs. Depending on the feedback paths from the accumulator to the frequency control inputs of the full adders, the effective denominator value can be increased or decreased to obtain the desired conversion ratio. The EFD feedback paths are chosen in conjunction with the numerator input value. It is possible to increase the effective denominator by replacing an existing xe2x80x981xe2x80x99 in the numerator with a complimentary carry out signal. It is possible to decrease the denominator by replacing a xe2x80x980xe2x80x99 in the numerator with a carry out signal. The actual implementation of this fractional divider for a programmable application is very difficult. Firstly there has to be a big mutiplexer for connecting any of the carry out or complimentary carryouts to any of the inputs of the full adder. Programming the fractional divider for any increments in the fractional division involves lot of calculations. This makes this approach not suitable where the fractional division contents have to be dynamically changed for example clock recovery.
One embodiment of this invention obviates the above disadvantages by providing a complete digital implementation of the fractional divider and thereby avoiding delay lines and noise due to analog components.
Another embodiment of the invention has a flexible scheme wherein both the division value and the fractional part are dynamically programmable to achieve a better fractional least count.
Another embodiment of this invention makes technology migration much simpler by implementing the frequency divider in any HDL (Hardware Definition Language).
Another embodiment of the invention is an improved fractional divider that provides high resolution without the need for any analog components comprising:
an integer value storage containing the integer part of the division value xe2x80x98Kxe2x80x99 connected to the input of a
programmable counter that is configured for a count value of xe2x80x98Kxe2x80x99 or xe2x80x98K+1xe2x80x99 depending upon the state of a count control signal and that generates the output signal as well a terminal count signal which is connected to an enable input of a
fractional accumulator that produces a count control signal on an addition overflow and has a first input connected to its result output and a second input connected to the output of a
fractional value storage, containing the fractional part of the divider value.
The said integer value storage is any digital value storage.
The said fractional accumulator is a multibit full adder, the number of bits depending on the desired resolution of said fractional divider.
The said digital value storage is a register.
The fractional value storage is any digital value storage.
The said digital value storage is a register.
The said integer value storage and said fractional value storage are connected to the data bus of a microprocessor or microcontroller based system for loading the integer part and fractional part of the division value respectively.